TSMC to Launch 20nm Pilot Production in 2012

Taipei, April 26, 2011 (CENS)--Taiwan Semiconductor Manufacturing Co. (TSMC) will put its 20nm process into pilot production sometime in the second half of 2012 as its first step into 450mm wafer era, according to the company's senior vice president in charge of research and development, S.Y. Chiang.

The senior vice president disclosed the process-technology roadmap yesterday at a forum, held in Taipei, addressing very-large scale integration (VLSI) technology.

As for 28nm process technology, Chiang pointed out that the company, which is recognized as the world's No.1 pure silicon foundry, will place the process on volume production lines in the second half of this year. The company has begun pilot run of this process technology in the second quarter of the year on some design tapeouts. Tapeout means the final step of IC design cycle at which the photomask of the IC is sent for manufacturing.

Chiang noted that 28nm process can turn out more than twice as many chips as 40nm can on the same wafer. He added the company will complete pilot production of the process on 70 tapeouts throughout this year.

Chiang estimated the Moore's Law, which is named after Intel Co-Founder Gordon E. Moore describing the number of transistors in an IC chip will double about every 18 months since the 1965 invention of IC, will remain applicable in the semiconductor industry at least until 7nm process is introduced.

He said in the future wafer foundries will not only shrink chip size but also system-on-chip size and the room for size-shrinkage technology to advance will remain ample.

Also, the room for cooperation between silicon foundries and chip assemblers, Chiang added, will grow bigger when sizes of single chips and system chips continue scaling down.