The Electronics Research & Service Organization (ERSO) of the government-backed Industrial Technology Research Institute (ITRI) recently debuted a new cost-effective wafer-level chip-scale package (WLCSP) technology that can eliminate at least four processes from current flip-chip packaging methods.

ERSO has won 17 patents in Taiwan and overseas on 11 unique WLCSP methods, most of which are based on a buffer-layer building framework. Instead of building the layer with complicated photolithographing and sputtering methods, ERSO's specialists have figured out a way to produce the polymer layer by simply putting one layer of the material upon another, a method they call "printing." "This is the simplest and cheapest of three extant methods," says Chen Wunyan, director of the Packaging Process Technology Division at ERSO's Advanced Process Technology Department.

The buffer layer is a critical part of the WLCSP technology. This soft layer is placed between the printed circuit board (PCB) and solder bumps to prevent the micron-thick conducting wires routing through the buffer from disconnecting from the bumps after repeated temperature-induced expansions and contractions during processing.

This layer is unnecessary when chips are packaged with traditional methods such as thin small-outline package (TSOP), currently the standard method for encasing memory chips. With the TSOP method, chip assemblers wrap up chips with thick epoxy resin after they are bundled with conducting pins, called lead frames within the industry, to connect circuits on chips to devices on boards. Since the solid resin protects the chips and secures the pins, thermal expansion does not break the joints between the lead frames and chips.

However, traditional package methods are costly because of additional processes including chip slicing, lead-frame bundling and encasing. Even flip-chip technology, a cousin technology of WLCSP, requires eight processes, including application of underfill encapsulants and attachment of interface substrates.


Simply Better


ERSO's WLCSP technology, by comparison, requires only four processes before the chips are sliced from the wafers: application of dielectric material, building of copper/aluminum interconnects, building buffer layers, and solder bumping. The polymer-constituted dielectric film acts as a shield that keeps air particles from the surface of the chips and also prevents contact between circuits.

The organization's technology is mainly designed for chips larger than 5mm x 5mm. "Usually, bigger objects have bigger linear coefficients of thermal expansion," explains Dr. Lo Weichung, manager of Chen's department.



WLCSP is considered to be the most cost-effective and reliable packaging method in the world today. It is also one of the most promising technologies in the chip-packaging market, which as a whole is projected to have a staggering 53.04% compound annual growth rate (CAGR) for the 1999-2004 period. More than 30 different types of packaging technology have been developed to date, with the solder-bump type considered the most workable method.

ERSO began developing WLCSP technology in 1999 with financial support from the Ministry of Economic Affairs (MOEA). Like other organizations across the world working on the technology, ERSO's department wanted to apply flip-chip packaging technology to smaller chips to help chip companies trim costs.

The flip-chip method has long been used on sophisticated chips such as microprocessors due to its high reliability. This method also enables chips to be packaged on wafers and eliminates the need for epoxy-resin encasing. However, a substrate board is needed as an interface between the PCBs and chips as these chips usually carry more circuits than are on the PCBs. An underfill encapsulant is therefore required to fill the gap between the substrate board and flip-side chip. These processes add costs. "So, WLCSP makes the expensive flip-chip technology less expensive by streamlining the processes," Chen emphasizes.


Reliable Solution


ERSO's Advanced Process Technology Department has proved that its technology meets design codes set by the JEDEC Solid State Technology Association (formerly known as the Joint Electron Device Engineering Council), the semiconductor engineering standardization body of the Electronic Industries Alliance (EIA), a trade association that represents the electronics industry. It has also proven that its technology works reliably.

Nevertheless, many chip assemblers have been hesitant to buy the technology. "Their concerns are mostly associated with the fact that chips made with the package technology retain their bare size, increasing risks of material-inventory backlogs," Chen explains.

His department hopes to license the technology first to assemblers of dynamic random access memory (DRAM) chips because Taiwan has been the world's third-largest supplier of the chips since at least 2001, with production value representing 17.8% of world's total last year. Usually, the assemblers keep one size of PCB in inventory for the chips since the mainstream TSOP method produces chips of one size, enabling the assemblers to easily calculate what inventory level they should maintain.

But different DRAM makers supply chips in different bare size, which will pose a big challenge to assemblers if they decide to adopt WLCSP technology, since they will need to prepare many specifically sized boards for each chip size.